(r1.1 vs. r1.37) The PSU MDL Wiki: Main Web

<<O>> Difference Topic MikeDebole (r1.37 - 03 Nov 2008 - MikeDebole)

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Michael V. DeBole

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Publications

Conference Papers

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Michael DeBole, Ramakrishnan Krishnan, Varsha Balakrishnan, Wenping Wang, Luo Hong, Yu Wang, Yuan Xie, Yu Cao, N. Vijaykrishnan. "A Framework for Estimating NBTI Degradation of Microarchitectural Components," to Appear in Proceedings of the 14th Asia and South Pacific Design Automation Conference(ASP-DAC), January 2009.

Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan. "A Criticality-Driven Microarchitectural Three Dimensional (3D) Floorplanner," to Appear in Proceedings of the 14th Asia and South Pacific Design Automation Conference(ASP-DAC), January 2009.

Kevin Irick, Michael DeBole, N. Vijaykrishnan, and Aman Gayasen. "A Hardware Efficient Support Vector Machine Architecture for FPGA," to Appear IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2008.

David Atienza, Giovanni De Micheli, Luca Benini, Jose L. Ayala, Pablo G. Del Valle, Michael DeBole, Vijay Narayanan. "Reliability-Aware Design for Nanometer-Scale Devices" in Proceedings of the 13th Asia and South Pacific Design Automation Conference(ASP-DAC), January 2008. (*Invited Paper)

Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.Talk

<<O>> Difference Topic MikeDebole (r1.36 - 06 May 2008 - MikeDebole)

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Michael V. DeBole

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Depart Date	Return Date	Destination	Purpose
2008
March 4	March 6	Yorktown Hights, NY	GSRC Spring Meeting

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June 7

June 12

Anaheim, CA

GSRC Meeting / DAC

Links

Gigascale System Research Center

<<O>> Difference Topic MikeDebole (r1.35 - 26 Apr 2008 - MikeDebole)

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Michael V. DeBole

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Links

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Gigascale System Research Corporation

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Gigascale System Research Center

<<O>> Difference Topic MikeDebole (r1.34 - 06 Mar 2008 - MikeDebole)

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Michael V. DeBole

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Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan and M.J. Irwin. "On-chip Bus Thermal Analysis and Optimization", accepted for publication in IEE Computer Design and Test, 2007.

Awards and Scholarships

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2006 Recipient of the Lockheed Martin Graduate Fellowship
2006 Recipient of the C. Norwood Wherry Memorial Graduate Fellowship
2006 (Spring) Lockheed Martin Design Award (Software Engineering)

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>

Recipient of the Lockheed Martin Graduate Fellowship
Recipient of the C. Norwood Wherry Memorial Graduate Fellowship
Lockheed Martin Design Award (Software Engineering)

Contact Information

<<O>> Difference Topic MikeDebole (r1.33 - 03 Mar 2008 - MikeDebole)

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Michael V. DeBole

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Conference Papers

David Atienza, Giovanni De Micheli, Luca Benini, Jose L. Ayala, Pablo G. Del Valle, Michael DeBole, Vijay Narayanan. "Reliability-Aware Design for Nanometer-Scale Devices" in Proceedings of the 13th Asia and South Pacific Design Automation Conference(ASP-DAC), January 2008. (*Invited Paper)

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Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.

>
>

Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.Talk

Journal Papers

Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan and M.J. Irwin. "On-chip Bus Thermal Analysis and Optimization", accepted for publication in IEE Computer Design and Test, 2007.

<<O>> Difference Topic MikeDebole (r1.32 - 25 Feb 2008 - MikeDebole)

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Michael V. DeBole

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Research

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As we begin to cross the threshold into the billion transistor era Multiprocessor Systems-on-Chips (MPSoC) are becoming ever-present, driving advancement in multiple application domains ranging from entertainment to medical devices. Consequently, MPSoC designers must be able to optimize a multi-constrained set comprised of performance, power consumption, reliability and cost. At the same time, as feature sizes shrink into the sub-micron regime, physical limitations and manufacturing variability are resulting in unreliable, power-hungry chips. To combat this, system simulations which take into consideration the interplay of performance, thermal characteristics, variability, and reliability effects from real-life workloads are becoming valuable when performing design space explorations of these next-generation architectures. However, the increase in complexity stemming from the need to profile complex modern processors, over extended periods of time, is placing a significant burden on the speed of traditional software simulators.

>
>

As we begin to cross the threshold into the billion transistor era, Multiprocessor Systems-on-Chips (MPSoC) are becoming ever-present, driving advancement in multiple application domains ranging from entertainment to medical devices. Consequently, MPSoC designers must be able to optimize a multi-constrained set comprised of performance, power consumption, reliability and cost. At the same time, as feature sizes shrink into the sub-micron regime, physical limitations and manufacturing variability are resulting in unreliable, power-hungry chips. To combat this, system simulations which take into consideration the interplay of performance, thermal characteristics, variability, and reliability effects from real-life workloads, are becoming valuable when performing design space explorations of these next-generation architectures. However, the increase in complexity stemming from the need to profile complex modern processors, over extended periods of time, is placing a significant burden on the speed of traditional software simulators.

My work has been motivated by these challenges and has led me to begin investigating a Virtual Platform (ViP) framework on FPGAs which can significantly speed up system profiling through system emulation. Currently, I am working towards building a general framework for the ViP and using it to characterize a multi-core implementation of the IEEE-754 (SPARC V8) architecture. Once in place the ViP will then permit a thorough investigation into alternative architectures and mitigation techniques to achieve the golden "design" polyptych of POWER, PERFORMANCE, RESILIENCY, and COST.

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Travel Schedule

Depart Date

Return Date

Destination

Purpose

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2007

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2008

March 4

March 6

Yorktown Hights, NY

GSRC Spring Meeting

<<O>> Difference Topic MikeDebole (r1.31 - 18 Feb 2008 - MikeDebole)

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Michael V. DeBole

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Travel Schedule

Depart Date	Return Date	Destination	Purpose
2007

Changed:

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May 31	August 24	Lausanne, Switzerland	Summer Appointment at EPFL
August 25	Sept 1	Amsterdam	FPL
Sept 14	Sept 14	Pittsburgh, PA	TTC Review
Sept 19	Sept 22	San Jose, CA	GSRC Annual Symposium

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March 4

March 6

Yorktown Hights, NY

GSRC Spring Meeting

Links

Gigascale System Research Corporation

<<O>> Difference Topic MikeDebole (r1.30 - 14 Feb 2008 - MikeDebole)

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Michael V. DeBole

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Publications

Conference Papers

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Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.

David Atienza, Giovanni De Micheli, Luca Benini, Jose L. Ayala, Pablo G. Del Valle, Michael DeBole, Vijay Narayanan. "Reliability-Aware Design for Nanometer-Scale Devices" in Proceedings of the 13th Asia and South Pacific Design Automation Conference(ASP-DAC), January 2008. (*Invited Paper)

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Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.

Journal Papers

Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan and M.J. Irwin. "On-chip Bus Thermal Analysis and Optimization", accepted for publication in IEE Computer Design and Test, 2007.

<<O>> Difference Topic MikeDebole (r1.29 - 25 Jan 2008 - MikeDebole)

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Michael V. DeBole

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Conference Papers

Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.

Added:

>
>

David Atienza, Giovanni De Micheli, Luca Benini, Jose L. Ayala, Pablo G. Del Valle, Michael DeBole, Vijay Narayanan. "Reliability-Aware Design for Nanometer-Scale Devices" in Proceedings of the 13th Asia and South Pacific Design Automation Conference(ASP-DAC), January 2008. (*Invited Paper)

Journal Papers

Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan and M.J. Irwin. "On-chip Bus Thermal Analysis and Optimization", accepted for publication in IEE Computer Design and Test, 2007.

<<O>> Difference Topic MikeDebole (r1.28 - 06 Oct 2007 - MikeDebole)

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Michael V. DeBole

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Publications

Conference Papers

Changed:

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Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," to appear in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.

>
>

Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.

Journal Papers

Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan and M.J. Irwin. "On-chip Bus Thermal Analysis and Optimization", accepted for publication in IEE Computer Design and Test, 2007.

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Sept 19

Sept 22

San Jose, CA

GSRC Annual Symposium

Links

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Gigascale System Research Corporation

<<O>> Difference Topic MikeDebole (r1.27 - 12 Sep 2007 - MikeDebole)

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Michael V. DeBole

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Contact Information

Email at PSU: debole AT cse DOT psu DOT edu

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Office : IST 354B, IST Building, Penn State, University Park, PA 16802

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Office : IST 351, IST Building, Penn State, University Park, PA 16802

Phone : +1–814–863–1047 (Office)

Travel Schedule

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2007
May 31	August 24	Lausanne, Switzerland	Summer Appointment at EPFL
August 25	Sept 1	Amsterdam	FPL

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Sept 14

Pittsburgh, PA

TTC Review

Sept 19

Sept 22

San Jose, CA

GSRC Annual Symposium

Links

<<O>> Difference Topic MikeDebole (r1.26 - 08 Sep 2007 - MikeDebole)

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Michael V. DeBole

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Contact Information

Email at PSU: debole AT cse DOT psu DOT edu

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Email at EPFL[Summer]: michael DOT debole AT epfl DOT ch

Office : IST 354B, IST Building, Penn State, University Park, PA 16802

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Phone : +1–814–863–7325 (Office)

I have an appointment at EPFL for the summer. Please contact me via e-mail.

>
>

Phone : +1–814–863–1047 (Office)

Travel Schedule

Depart Date

Return Date

Destination

Purpose

<<O>> Difference Topic MikeDebole (r1.25 - 23 Aug 2007 - MikeDebole)

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Michael V. DeBole

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Research

Changed:

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As we begin to cross the threshold into the billion transistor era Multiprocessor Systems-on-Chips (MPSoC) are becoming ever-present, driving advancement in multiple application domains ranging from entertainment to medical devices. Consequently, MPSoC designers must be able to optimize a multi-constrained set comprised of performance, power consumption, reliability and cost. At the same time, as feature sizes shrink into the sub-micron regime, physical limitations and manufacturing variability are resulting in unreliable, power-hungry chips. To combat this, system simulations which take into consideration the interplay of performance, thermal characteristics, variability, and reliability effects from real-life workloads are becoming valuable when performing design space explorations of these next-generation architectures. However, the increase in complexity stemming from the need to profile complex modern processors, over extended periods of time, is placing a significant burden on the speed of traditional software simulators. My work has been motivated by these challenges and has led me to begin investigating a Virtual Platform (ViP) framework on FPGAs which can significantly speed up system profiling through system emulation. Currently, I am working towards building a general framework for the ViP and using it to characterize a multi-core implementation of the IEEE-754 (SPARC V8) architecture. Once in place the ViP will then permit a thorough investigation into alternative architectures and mitigation techniques to achieve the golden "design" polyptych of POWER, PERFORMANCE, RESILIENCY, and COST.

>
>

As we begin to cross the threshold into the billion transistor era Multiprocessor Systems-on-Chips (MPSoC) are becoming ever-present, driving advancement in multiple application domains ranging from entertainment to medical devices. Consequently, MPSoC designers must be able to optimize a multi-constrained set comprised of performance, power consumption, reliability and cost. At the same time, as feature sizes shrink into the sub-micron regime, physical limitations and manufacturing variability are resulting in unreliable, power-hungry chips. To combat this, system simulations which take into consideration the interplay of performance, thermal characteristics, variability, and reliability effects from real-life workloads are becoming valuable when performing design space explorations of these next-generation architectures. However, the increase in complexity stemming from the need to profile complex modern processors, over extended periods of time, is placing a significant burden on the speed of traditional software simulators.

My work has been motivated by these challenges and has led me to begin investigating a Virtual Platform (ViP) framework on FPGAs which can significantly speed up system profiling through system emulation. Currently, I am working towards building a general framework for the ViP and using it to characterize a multi-core implementation of the IEEE-754 (SPARC V8) architecture. Once in place the ViP will then permit a thorough investigation into alternative architectures and mitigation techniques to achieve the golden "design" polyptych of POWER, PERFORMANCE, RESILIENCY, and COST.

In other work I have also developed hardware implementations of Neural Networks and Support Vector Machines as a means for detection and classification within images and video. In this work we utilized FPGA's as the primary means to realize these architectures.

<<O>> Difference Topic MikeDebole (r1.24 - 22 Aug 2007 - MikeDebole)

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Michael V. DeBole

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Research

Changed:

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My research interests include Computer Architectures, Multi-Processor System-on-Chips(MPSoCs), and Field Programmable Gate Arrays(FPGAs). More specifically I am interested in the emulation of future MPSoC Architectures within FPGAs for measuring the golden "design" triptych of POWER, PERFORMANCE, and RELIABILITY.

>
>

As we begin to cross the threshold into the billion transistor era Multiprocessor Systems-on-Chips (MPSoC) are becoming ever-present, driving advancement in multiple application domains ranging from entertainment to medical devices. Consequently, MPSoC designers must be able to optimize a multi-constrained set comprised of performance, power consumption, reliability and cost. At the same time, as feature sizes shrink into the sub-micron regime, physical limitations and manufacturing variability are resulting in unreliable, power-hungry chips. To combat this, system simulations which take into consideration the interplay of performance, thermal characteristics, variability, and reliability effects from real-life workloads are becoming valuable when performing design space explorations of these next-generation architectures. However, the increase in complexity stemming from the need to profile complex modern processors, over extended periods of time, is placing a significant burden on the speed of traditional software simulators. My work has been motivated by these challenges and has led me to begin investigating a Virtual Platform (ViP) framework on FPGAs which can significantly speed up system profiling through system emulation. Currently, I am working towards building a general framework for the ViP and using it to characterize a multi-core implementation of the IEEE-754 (SPARC V8) architecture. Once in place the ViP will then permit a thorough investigation into alternative architectures and mitigation techniques to achieve the golden "design" polyptych of POWER, PERFORMANCE, RESILIENCY, and COST.

In other work I have also developed hardware implementations of Neural Networks and Support Vector Machines as a means for detection and classification within images and video. In this work we utilized FPGA's as the primary means to realize these architectures.

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VLSI design for low power, low cost, and high performance
Embedded Systems
Statistical learning theory and machine learning.

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Computer Architecture

Publications

<<O>> Difference Topic MikeDebole (r1.23 - 17 Aug 2007 - MikeDebole)

META TOPICPARENT	TWikiUsers

Michael V. DeBole

My name is Michael DeBole and I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University. I received my B.Sc. degree in Computer Engineering from The Pennsylvania State University in 2006 (with a minor in Engineering Leadership and Development).

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I currently work in the Microsystems Design Laboratory(MDL) within the Computer Science and Engineering Department. My research advisor is Dr. Vijaykrishnan Narayanan.

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I currently work in the Microsystems Design Laboratory(MDL) within the Computer Science and Engineering Department. I am co-advised by Dr. Vijaykrishnan Narayanan and Dr. Yuan Xie.

Research

<<O>> Difference Topic MikeDebole (r1.22 - 16 Aug 2007 - MikeDebole)

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Michael V. DeBole

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Conference Papers

Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," to appear in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.

Added:

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Journal Papers

Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan and M.J. Irwin. "On-chip Bus Thermal Analysis and Optimization", accepted for publication in IEE Computer Design and Test, 2007.

Awards and Scholarships

2006 Recipient of the Lockheed Martin Graduate Fellowship
2006 Recipient of the C. Norwood Wherry Memorial Graduate Fellowship

<<O>> Difference Topic MikeDebole (r1.21 - 08 Aug 2007 - MikeDebole)

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Michael V. DeBole

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Travel Schedule

Depart Date	Return Date	Destination	Purpose
2007

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May 31

Sept 1

EPFL / Amsterdam

Summer Appointment / FPL

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May 31	August 24	Lausanne, Switzerland	Summer Appointment at EPFL
August 25	Sept 1	Amsterdam	FPL

Sept 19

Sept 22

San Jose, CA

GSRC Annual Symposium

Links

<<O>> Difference Topic MikeDebole (r1.20 - 03 Aug 2007 - MikeDebole)

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Michael V. DeBole

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Office : IST 354B, IST Building, Penn State, University Park, PA 16802
Phone : +1–814–863–7325 (Office)

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I have an appointment at EPFL for the summer. Please contact me via e-mail.

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Travel Schedule

Depart Date	Return Date	Destination	Purpose
2007
May 31	Sept 1	EPFL / Amsterdam	Summer Appointment / FPL
Sept 19	Sept 22	San Jose, CA	GSRC Annual Symposium

Links

<<O>> Difference Topic MikeDebole (r1.19 - 11 Jun 2007 - MikeDebole)

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Michael V. DeBole

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Embedded Systems
Statistical learning theory and machine learning.

Added:

>
>

Publications

Conference Papers

Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," to appear in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.

Awards and Scholarships

2006 Recipient of the Lockheed Martin Graduate Fellowship
2006 Recipient of the C. Norwood Wherry Memorial Graduate Fellowship

<<O>> Difference Topic MikeDebole (r1.18 - 07 Jun 2007 - MikeDebole)

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Michael V. DeBole

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Contact Information

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Email: debole AT cse DOT psu DOT edu

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Email at PSU: debole AT cse DOT psu DOT edu
Email at EPFL[Summer]: michael DOT debole AT epfl DOT ch

Office : IST 354B, IST Building, Penn State, University Park, PA 16802
Phone : +1–814–863–7325 (Office)

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I have an appointment at EPFL for the summer. Please contact me via e-mail.

Links

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LSI at EPFL

<<O>> Difference Topic MikeDebole (r1.17 - 24 May 2007 - MikeDebole)

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Michael V. DeBole

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My name is Michael DeBole and I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University. I recived my B.Sc. degree in Computer Engineering from The Pennsylvania State University in 2006 (with a minor in Engineering Leadership and Development).

>
>

My name is Michael DeBole and I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University. I received my B.Sc. degree in Computer Engineering from The Pennsylvania State University in 2006 (with a minor in Engineering Leadership and Development).

I currently work in the Microsystems Design Laboratory(MDL) within the Computer Science and Engineering Department. My research advisor is Dr. Vijaykrishnan Narayanan.

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<<O>> Difference Topic MikeDebole (r1.16 - 22 May 2007 - MikeDebole)

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Michael V. DeBole

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Office : IST 354B, IST Building, Penn State, University Park, PA 16802
Phone : +1–814–863–7325 (Office)

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I have an appointment at EPFL for the summer. Please contact me via e-mail.

Links

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<<O>> Difference Topic MikeDebole (r1.15 - 27 Apr 2007 - MikeDebole)

  META TOPICPARENT  TWikiUsers 

  Michael V. DeBole
-<
<
+     I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University where I work in the Microsystems Design Laboratory(MDL). My research advisor is Dr. Vijaykrishnan Narayanan.
->
>
+     My name is Michael DeBole and I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University. I recived my B.Sc. degree in Computer Engineering from  The Pennsylvania State University in 2006 (with a minor in Engineering Leadership and Development).

    I currently work in the Microsystems Design Laboratory(MDL) within the Computer Science and Engineering Department. My research advisor is Dr. Vijaykrishnan Narayanan.
   Research
-<
<
+     My research interests include computer architecture and it's integration within signal and image processing. More specifically in the area     
     of pattern classification and computer learning. Recently I have been looking into hardware implementations of neural networks and support vector machines as a means 
     for detection and classification within images and video. I have also been exploring FPGA's as a viable means in which these architectures may be implemented.
->
>
+     My research interests include Computer Architectures, Multi-Processor System-on-Chips(MPSoCs), and Field Programmable Gate Arrays(FPGAs). More specifically I am interested in the emulation of future MPSoC Architectures within FPGAs for measuring the golden "design" triptych of POWER, PERFORMANCE, and RELIABILITY.

In other work I have also developed hardware implementations of Neural Networks and Support Vector Machines as a means for detection and classification within images and video. In this work we utilized FPGA's as the primary means to realize these architectures.
     My research interests also include
-<
<
+ Statistical learning theory and machine learning.
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>
+ FPGA Accelerators for Scientific Computing Applications

 FPGA's as a complete solution for system-on-chip (Hardware/Software Co-Design)
  VLSI design for low power, low cost, and high performance

 Embedded Systems
-<
<
+ FPGA's as a complete design solution for system-on-chip (Hardware/Software Co-Design)
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>
+ Statistical learning theory and machine learning.
   Awards and Scholarships 

 2006 Recipient of the Lockheed Martin Graduate Fellowship
  Phone : +1–814–863–7325 (Office)



  Links
-<
<
+ Lockheed Martin
  Video Mining

 The Technology Collaborative

<<O>> Difference Topic MikeDebole (r1.14 - 15 Jan 2007 - MikeDebole)

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Michael V. DeBole

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Research

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My research interests include computer architecture, embedded systems, and facilitating their use within signal and image processing. More specifically in the area

>
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My research interests include computer architecture and it's integration within signal and image processing. More specifically in the area

of pattern classification and computer learning. Recently I have been looking into hardware implementations of neural networks and support vector machines as a means for detection and classification within images and video. I have also been exploring FPGA's as a viable means in which these architectures may be implemented.

Added:

>
>

My research interests also include

Statistical learning theory and machine learning.
VLSI design for low power, low cost, and high performance
Embedded Systems
FPGA's as a complete design solution for system-on-chip (Hardware/Software Co-Design)

Awards and Scholarships

2006 Recipient of the Lockheed Martin Graduate Fellowship
2006 Recipient of the C. Norwood Wherry Memorial Graduate Fellowship

<<O>> Difference Topic MikeDebole (r1.13 - 15 Jan 2007 - MikeDebole)

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Michael V. DeBole

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Research

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My research interests include computer architecture and embedded systems. Recently I have been looking into implementing face detection and gender recognition in FPGA's. I am also currenty working on an FPGA implementation of a fast matrix multiplier for scientific computing applications.

>
>

My research interests include computer architecture, embedded systems, and facilitating their use within signal and image processing. More specifically in the area of pattern classification and computer learning. Recently I have been looking into hardware implementations of neural networks and support vector machines as a means for detection and classification within images and video. I have also been exploring FPGA's as a viable means in which these architectures may be implemented.

Awards and Scholarships

2006 Recipient of the Lockheed Martin Graduate Fellowship

Changed:

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2006 Recipient of the Penn State College of Engineering Fellowship

>
>

2006 Recipient of the C. Norwood Wherry Memorial Graduate Fellowship

2006 (Spring) Lockheed Martin Design Award (Software Engineering)

<<O>> Difference Topic MikeDebole (r1.12 - 31 Oct 2006 - MikeDebole)

META TOPICPARENT	TWikiUsers

Michael V. DeBole

I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University where I work in the Microsystems Design Laboratory(MDL). My research advisor is Dr. Vijaykrishnan Narayanan.

Deleted:

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Contact Information

Email: debole AT cse DOT psu DOT edu
Office : IST 354B, IST Building, Penn State, University Park, PA 16802
Phone : +1–814–863–7325 (Office)

Research

My research interests include computer architecture and embedded systems. Recently I have been looking into implementing face detection and gender recognition in FPGA's. I am also currenty working on an FPGA implementation of a fast matrix multiplier for scientific computing applications.

Line: 22 to 15

2006 Recipient of the Penn State College of Engineering Fellowship
2006 (Spring) Lockheed Martin Design Award (Software Engineering)

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Contact Information

Email: debole AT cse DOT psu DOT edu
Office : IST 354B, IST Building, Penn State, University Park, PA 16802
Phone : +1–814–863–7325 (Office)

Links

<<O>> Difference Topic MikeDebole (r1.11 - 30 Oct 2006 - MikeDebole)

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Michael V. DeBole

I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University where I work in the Microsystems Design Laboratory(MDL). My research advisor is Dr. Vijaykrishnan Narayanan.

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My research interests include computer architecture and embedded systems. Recently I have been looking into implementing face detection and gender recognition in FPGA's. I am also currenty working on an FPGA implementation of a fast matrix multiplier for scientific computing applications.

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Awards and Scholarships

2006 Recipient of the Lockheed Martin Graduate Fellowship
2006 Recipient of the Penn State College of Engineering Fellowship
2006 (Spring) Lockheed Martin Design Award (Software Engineering)

Links

<<O>> Difference Topic MikeDebole (r1.10 - 06 Oct 2006 - MikeDebole)

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Michael V. DeBole

I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University where I work in the Microsystems Design Laboratory(MDL). My research advisor is Dr. Vijaykrishnan Narayanan.

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- Set EDITBOXSTYLE = width: 99%
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- Set ALLOWTOPICCHANGE = MikeDebole

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Optionally allow web-level editing blocks creating new topics, changing topics or attaching files
- Set ALLOWWEBCHANGE = MikeDebole

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<<O>> Difference Topic MikeDebole (r1.9 - 02 Oct 2006 - MikeDebole)

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Michael V. DeBole

I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University where I work in the Microsystems Design Laboratory(MDL). My research advisor is Dr. Vijaykrishnan Narayanan.

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My research interests include computer architecture and embedded systems. Recently I have been looking into face detection and its implementation in FPGA's. I am also looking into a FPGA implementation of a fast matrix multiplier for scientific computing applications.

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Contact Information

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Research

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Coming Soon !

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My research interests include computer architecture and embedded systems. Recently I have been looking into implementing face detection and gender recognition in FPGA's. I am also currenty working on an FPGA implementation of a fast matrix multiplier for scientific computing applications.

Links

Lockheed Martin

<<O>> Difference Topic MikeDebole (r1.8 - 22 Sep 2006 - MikeDebole)

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Michael V. DeBole

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I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University where I work in the Microsystems Design Laboratory(MDL). My research advisor is Dr. Vijaykrishnan Narayanan.

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I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University. I work in the Microsystems Design Laboratory(MDL) within the CSE department where my current research advisor is Dr. Vijaykrishnan Narayanan. I am also the 2006 recipient of the Lockheed Martin Graduate Fellowship.

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My research interests include computer architecture and embedded systems. Recently I have been looking into face detection and its implementation in FPGA's. I am also looking into a FPGA implementation of a fast matrix multiplier for scientific computing applications.

Contact Information

<<O>> Difference Topic MikeDebole (r1.7 - 22 Sep 2006 - MikeDebole)

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Michael V. DeBole

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I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University. I work in the Microsystems Design Laboratory(MDL) within the CSE department where my current research advisor is Dr. Vijaykrishnan Narayanan. I am also the 2006 recipient of the Lockheed Martin Graduate Fellowship.

Contact Information

<<O>> Difference Topic MikeDebole (r1.6 - 19 Sep 2006 - MikeDebole)

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Michael V. DeBole

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Contact Information

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Email: debole at cse dot psu dot edu

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Email: debole AT cse DOT psu DOT edu

Office : IST 354B, IST Building, Penn State, University Park, PA 16802
Phone : +1–814–863–7325 (Office)

<<O>> Difference Topic MikeDebole (r1.5 - 19 Sep 2006 - MikeDebole)

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Michael V. DeBole

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Contact Information

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Contact Information

Email: debole at cse dot psu dot edu
Office : IST 354B, IST Building, Penn State, University Park, PA 16802
Phone : +1–814–863–7325 (Office)

Research

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Coming Soon !

Links

<!-- Personal Preferences (details in TWikiVariables)

<<O>> Difference Topic MikeDebole (r1.4 - 18 Sep 2006 - AdityaYsv)

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Michael V. DeBole

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Research

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Show tool-tip topic info on mouse-over of WikiWord links, on or off: (see details in TWikiPreferences)
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Horizontal size of text edit box:
- Set EDITBOXWIDTH = 70
Vertical size of text edit box:
- Set EDITBOXHEIGHT = 22
Style of text edit box. width: 99% for full window width (default), width: auto to disable.
- Set EDITBOXSTYLE = width: 99%
Optionally write protect your home page: (set it to your WikiName)
- Set ALLOWTOPICCHANGE = MikeDebole

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<<O>> Difference Topic MikeDebole (r1.3 - 01 Sep 2006 - MikeDebole)

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Michael V. DeBole

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My Links

WelcomeGuest to learn TWiki
Sandbox web to try out TWiki
MikeDeboleSandbox just for me

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Contact Information

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Personal Preferences (details in TWikiVariables)

Show tool-tip topic info on mouse-over of WikiWord links, on or off: (see details in TWikiPreferences)
- Set LINKTOOLTIPINFO = off
Horizontal size of text edit box:
- Set EDITBOXWIDTH = 70
Vertical size of text edit box:
- Set EDITBOXHEIGHT = 22
Style of text edit box. width: 99% for full window width (default), width: auto to disable.
- Set EDITBOXSTYLE = width: 99%
Optionally write protect your home page: (set it to your WikiName)
- Set ALLOWTOPICCHANGE = MikeDebole

Changed:

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Related topics

ChangePassword^?
TWikiPreferences has site-level preferences of The PSU CSE TWiki.
WebPreferences has preferences of the The PSU CSE TWiki.Main web.
TWikiUsers has a list of other TWiki users.

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Research

<<O>> Difference Topic MikeDebole (r1.2 - 01 Sep 2006 - MikeDebole)

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Michael V. DeBole

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Name: Michael DeBole^?
Email: debole@cse.psu.edu
Company Name:
Company URL:
Country: USA
Comment:

My Links

WelcomeGuest to learn TWiki

<<O>> Difference Topic MikeDebole (r1.1 - 31 Aug 2006 - MikeDebole)

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META TOPICPARENT	TWikiUsers

Name: Michael DeBole^?
Email: debole@cse.psu.edu
Company Name:
Company URL:
Country: USA
Comment:

My Links

WelcomeGuest to learn TWiki
Sandbox web to try out TWiki
MikeDeboleSandbox just for me

Personal Preferences (details in TWikiVariables)

Show tool-tip topic info on mouse-over of WikiWord links, on or off: (see details in TWikiPreferences)
- Set LINKTOOLTIPINFO = off
Horizontal size of text edit box:
- Set EDITBOXWIDTH = 70
Vertical size of text edit box:
- Set EDITBOXHEIGHT = 22
Style of text edit box. width: 99% for full window width (default), width: auto to disable.
- Set EDITBOXSTYLE = width: 99%
Optionally write protect your home page: (set it to your WikiName)
- Set ALLOWTOPICCHANGE = MikeDebole

Related topics

ChangePassword^?
TWikiPreferences has site-level preferences of The PSU CSE TWiki.
WebPreferences has preferences of the The PSU CSE TWiki.Main web.
TWikiUsers has a list of other TWiki users.