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  • K. Irick, T. Theocharides, N. Vijaykrishnan, M. J. Irwin, A Real Time Embedded Face Dector on FPGA, Asilomar Conference on Signals, Systems, and Computers, pp 917-920.
  • I. Kadayif, M. Kandemir, Data Space-oriented Tiling for Enhancing Locality, to appear in ACM Transactions on Embedded Computing Systems.
  • J. Ramanujam, J. Hong, M. Kandemir, A. Narayan, Estimating and Reducing the Memory Requirements of Signal Processing Codes for Embedded Processor Systems, to appear in IEEE Trans. on Signal Processing.
  • J. Lee, N. Vijaykrishnan, M. J. Irwin, Block-Based Frequency Scalable Technique for Efficient Hierarchical Coding, to appear in IEEE Trans. on Signal Processing.
  • J. Lee, N. Vijaykrishnan, M. J. Irwin, W. Wolf, An Efficient Architecture for Motion Estimation and Compensation in the Transform Domain, to appear in IEEE Trans. on Circuits and Systems for Video Technology.
  • S. Kim, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Exploiting Temporal Loads for Low Latency and High Bandwidth Memory, to appear in IEE Proceedings: Computers and Digital Techniques.
  • J. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, Analyzing Data Reuse for Cache Reconfiguration, to appear in ACM Trans. on Embedded Computing Systems.
  • J. Lee, N. Vijaykrishnan, M. J. Irwin, Block-Based Frequency Scalable Technique for Efficient Hierarchical Coding, IEEE Trans. on Signal Processing, 54(7):2559-2566, Jul. 2006.
  • J. Lee, N. Vijaykrishnan, M. J. Irwin, Efficient VLSI Implementation of Inverse Discrete Cosine Transform, IEEE Trans. on Circuits and Systems for Video Technology, 16(5):655-662, May 2006.
  • T. Theocharides, N. Vijaykrishnan, M. J. Irwin, A Parallel Architecture for Hardware Face Detection, _Proc. of the Symposium on VLSI, Mar. 2006.
  • J. Lee., N. Vijaykrishnan, M. J. Irwin, W. Wolf, An Efficient Architecture for Motion Estimation and Compensation in the Transform Domain, IEEE Trans. on Circuits and Systems for Video Technology, 16(2):191-201, Feb. 2006.

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