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CSE 477. VLSI DIGITAL CIRCUITS (3:2:3) Digital integrated circuit design, layout, simulation, and fabrication; VLSI design techniques and system architecture; computer-aided design tools and techniques. Prerequisite: CSE 471, E E 310.
Powerpoint lecture slides are below (please check out the "read me" file first) ...
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| I | Attachment  | Action | Size | Date | Who | Comment |
|---|---|---|---|---|---|---|
 | cse477-1intro.ppt | manage | 1115.0 K | 05 Oct 2005 - 16:52 | MaryJaneIrwin | Introduction |
| | cse477readme.ppt | manage | 102.5 K | 05 Oct 2005 - 16:53 | MaryJaneIrwin | Read me first |
| | cse477-2metrics.ppt | manage | 404.0 K | 05 Oct 2005 - 16:54 | MaryJaneIrwin | Design metrics |
| | cse477-3MOStran.ppt | manage | 446.5 K | 05 Oct 2005 - 16:55 | MaryJaneIrwin | The MOS transistor |
| | cse477-4invstatic.ppt | manage | 293.5 K | 05 Oct 2005 - 16:55 | MaryJaneIrwin | The CMOS inverter - static view |
| | cse477-5fab.ppt | manage | 1740.5 K | 05 Oct 2005 - 16:56 | MaryJaneIrwin | Frabrication and design rules |
| | cse477-6staticlogic.ppt | manage | 336.5 K | 05 Oct 2005 - 16:56 | MaryJaneIrwin | Static CMOS logic |
| | cse477-7passtranlogic.ppt | manage | 451.0 K | 05 Oct 2005 - 16:57 | MaryJaneIrwin | Pass transistor logic |
| | cse477-8capacitance.ppt | manage | 361.5 K | 05 Oct 2005 - 16:57 | MaryJaneIrwin | Transistor and wire capacitances |
| | cse477-9resistance.ppt | manage | 397.0 K | 05 Oct 2005 - 16:58 | MaryJaneIrwin | Transistor and wire resistances |
| | cse477-10invdynamic.ppt | manage | 262.5 K | 05 Oct 2005 - 16:58 | MaryJaneIrwin | The CMOS inverter - dynamic view |
| | cse477-11speed.ppt | manage | 496.0 K | 05 Oct 2005 - 16:59 | MaryJaneIrwin | Designing for speed |
| | cse477-1213logicpower.ppt | manage | 1158.0 K | 05 Oct 2005 - 16:59 | MaryJaneIrwin | Designing for low power |
| | cse477-1516dynlogic.ppt | manage | 662.5 K | 05 Oct 2005 - 17:00 | MaryJaneIrwin | Dynamic CMOS logic |
| | cse477-17staticseq.ppt | manage | 473.5 K | 05 Oct 2005 - 17:01 | MaryJaneIrwin | Static sequential CMOS |
| | cse477-18dynamicseq.ppt | manage | 543.0 K | 05 Oct 2005 - 17:01 | MaryJaneIrwin | Dynamic sequential CMOS |
| | cse477-19timing.ppt | manage | 1486.5 K | 05 Oct 2005 - 17:02 | MaryJaneIrwin | Timing issues |
| | cse477-20adders.ppt | manage | 814.0 K | 05 Oct 2005 - 17:02 | MaryJaneIrwin | CMOS adders |
| | cse477-21multipliers.ppt | manage | 258.5 K | 05 Oct 2005 - 17:03 | MaryJaneIrwin | CMOS multipliers |
| | cse477-22shifters.ppt | manage | 619.0 K | 05 Oct 2005 - 17:03 | MaryJaneIrwin | CMOS shifters |
| | cse477-23memories.ppt | manage | 355.5 K | 05 Oct 2005 - 17:04 | MaryJaneIrwin | Memory architectures |
| | cse477-24memcores.ppt | manage | 391.5 K | 05 Oct 2005 - 17:04 | MaryJaneIrwin | Memory core design |
| | cse477-25memperipherals.ppt | manage | 260.0 K | 05 Oct 2005 - 17:05 | MaryJaneIrwin | Memory peripherals design |
| | cse477-26systempower.ppt | manage | 366.0 K | 05 Oct 2005 - 17:05 | MaryJaneIrwin | System level power issues |
| | cse477-27sysinterconnect.ppt | manage | 205.5 K | 05 Oct 2005 - 17:06 | MaryJaneIrwin | System level interconnect issues |
| | cse477-28dft.ppt | manage | 304.5 K | 05 Oct 2005 - 17:06 | MaryJaneIrwin | Design for test |
| | cse477-29scaling.ppt | manage | 386.5 K | 05 Oct 2005 - 17:07 | MaryJaneIrwin | Scaling considerations |
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Revisions: | r1.1 | Total page history | Backlinks
Revisions: | r1.1 | Total page history | Backlinks