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  • I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, I. Kolcu, Reducing Energy Consumption in Chip Multiprocessors using Workload Variation, Ultra-Low Power Electronics and Design, pp. 123-140, Ed. by Macii, 2004.
  • M. Kandemir, M. J. Irwin, G. Chen, I. Kolcu, Banked Scratch-pad Memory Management for Reducing Leakage Energy Consumption, Proc. of ICCAD’04, pp. 120-124, Nov. 2004.
  • Y-F. Tsai, D. Duarte, N. Vijaykrishnan, M. J. Irwin, Characterization and Modeling of Run-Time Techniques for Leakage Power Reduction, IEEE Trans. on VLSI Systems, 12(11):1221-1233, Nov. 2004.
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, Field-level Analysis for Heap Space Optimization in Embedded Java, Proc. of the Inter. Symp. on Memory Management (ISMM'04), pp. 131-142, Oct. 2004.
  • W. Hung, C. Addoquay, T. Theocharides, Y. Xie, N. Vijaykrishnan, M. J. Irwin, Thermal Aware IP Virtualization and Placement for Networks On Chip Architecture, Proc. of ICCD’04, pp. 430-437, Oct. 2004.
  • Y-F. Tsai, A. Hegde, N. Vijaykrishnan, M. J. Irwin, T. Theocharides, ChipPower: An Architecture-Level Leakage Simulator, Proc. of the Systems-on-Chip Conf. (SoCC’04), pp. 395-398, Sep. 2004.
  • G. Chen, B. T. Kang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, R. Chandramouli, Studying Energy Tradeoffs in Off-loading Computation/Compilation in Java-enabled Mobile Devices, IEEE Trans. on Parallel and Distributed Systems, 15(9):795-809, Sep. 2004.
  • V. De La Luz, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, Exploring the Possibility of Operating in the Compressed Domain, Proc. of Euro-Par'04, Springer-Verlag LNCS 3149(1):507-515, Aug.-Sept. 2004.
  • M. Kandemir, O. Ozturk, M. J. Irwin, I. Kolcu, Using Data Compression to Increase Energy Savings in Multi-bank Memories, Proc. of the Inter. Conf. on Parallel and Distributed Computing (Euro-Par'04), Springer-Verlag LNCS 3149(1):310-317, Aug.-Sep. 2004.
  • M. J. Irwin, L. Benini, N. Vijaykrishnan, M. Kandemir, Techniques for Designing Energy-aware MPSoCs, Multiprocessor Systems-on-Chips, Chpt. 2, pp. 21-47, Ed. by Jerraya and Wolf, Sep. 2004.
  • A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, T. Tuan, A Dual-Vdd Low Power FPGA Architecture, Proc. of the Conf. on Field-Programmable Logic and its Applications (FPL), Springer-Verlag LNCS 3203(1): 145-147, Aug. 2004.
  • W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Y. Tsai, Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing, Proc. of ISLPED’04, pp. 144-159, Aug. 2004.
  • H. Saputra, G. Chen, R. Brooks, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Code Protection for Resource-constrained Embedded Devices, Proc. of the Conf. on Languages, Compilers, and Tools for Embedded Systems (LCTES '04), pp. 240-248, Jun. 2004.
  • O. Ozturk, M. Kandemir, I. Demirkiran, G. Chen, M. J. Irwin, Data Compression for Improving SPM Behavior, Proc. of DAC'04, pp. 401-406, Jun. 2004.
  • Y-F. Tsai, D. Duarte, N. Vijaykrishnan, M.J. Irwin, Impact of Process Scaling on the Efficacy of Leakage Reduction Scheme, Proc. of Conf. on IC Design and Technology, pp. 3-11, May 2004.
  • A. Parikh, S. Kim, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, Instruction Scheduling for Low Power, Journal of VLSI Signal Processing Systems, 37(1):129-150, May 2004.
  • O. Ozturk, M. Kandemir, M. J. Irwin, I. Kolcu, Tuning Data Replication for Improving Behavior of MPSoC Applications, Proc. of GLSVLSI'04, pp. 170-173 , Apr. 2004.
  • W. Zhang, J. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, Reducing Instruction Cache Energy Consumption using a Compiler-Based Strategy, ACM Trans. on Architecture and Code Optimization, 1(1):3-33, Mar. 2004.
  • M. Kandemir, J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif, A. Parikh, A Compiler Based Approach for Dynamically Managing Scratch-pad Memories in Embedded Systems, IEEE Trans. on CAD, 23(2):243-260, Feb. 2004.
  • A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, T. Tuan, Reducing Leakage Energy in FPGAs Using Region-constrained Placement, Proc. of the ACM Inter. Symp. on Field-Programmable Gate Arrays (FPGA'04), pp. 51-58, Feb 2004.
  • I. Kadayif, I. Kolcu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessor, Proc. of DATE’04, pp. 1158-1163, Feb 2004.
  • J. Hu, N. Vijaykrishnan, S. Kim, M. Kandemir, M. J. Irwin, Scheduling Reusable Instructions for Power Reduction, Proc. of DATE'04, pp. 148-153, Feb. 2004. slides.pdf
  • J. Hu, N. Vijaykrishnan, M. J. Irwin, Exploring Wakeup-Free Instruction Scheduling, Proc. of HPCA-10, pp. 232-243, Feb 2004. slides.pdf
  • M. Derenzo, M. J. Irwin, N. Vijaykrishnan, Designing Leakage-Aware Multipliers, Proc. of VLSI Design, pp. 654-657, Jan 2004.
  • S. Kim, S. Tomar, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Energy-Efficient Java Execution Using Local Memory and Object Co-location, IEE Proceedings: Computers and Digital Techniques, 151(1):33-42, Jan. 2004.

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