• N. Vijaykrishnan, M. J. Irwin, M. Kandemir, L. Li, G. Chen, B. T. Kang, Designing Energy-aware Sensor Systems, in Frontiers in Distributed Sensor Networks, pp. 653-666, Ed. by Brooks and Iyengar, 2005.
• H. Saputra, N. Vijaykrishnan, M. Kandemir, R. Brooks, M. J. Irwin, An Energy-aware Approach for Sensor Data Communication, in Frontiers in Distributed Sensor Networks, pp. 697-720, Ed. by Brooks and Iyengar, 2005.
• I. Kadayif, M. Kandemir, A. Choudhary, M. Karakoy, N. Vijaykrishnan, M. J. Irwin, Compiler-directed Communication Energy Optimizations for Microsensor Networks, in Frontiers in Distributed Sensor Networks, pp. 711-734, Ed. by Brooks and Iyengar, 2005.
• M. J. Irwin, L. Benini, N. Vijaykrishnan, M. Kandemir, Energy-aware MPSoCs, in Multiprocessor Systems-on-Chips, pp. 21-48, Ed. by Jerraya and Wolf, 2005.
• T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, Networks on Chip: Interconnects for the Next Generation Systems on Chip, in Advances in Computers, 63(1):35-89, Ed. by Zelkowtiz and Hurson, 2005.
• I. Kadayif., M. Kandemir, G. Chen, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam, Compiler-directed High-level Energy Estimation and Optimization, ACM Trans. on Embedded Computing Systems, 4(4):819-850, Nov. 2005.
• W. Hung, G. Link, Y. Xie, N. Vijaykrishnan, N. Dhanwada, J. Conner, Temperature-Aware Voltage Islands Architecting in System-on-Chip Design, Proc. of ICCD'05, Oct. 2005.
• S. H. K. Narayanan, G. Chen, M. Kandemir and Y. Xie. Temperature-sensitive loop parallelization for chip multiprocessors. In Proc. IEEE International Conference on Computer Design, pp. 677-682, Oct. 2005. PDF PPT
• M. Kandemir, M. J. Irwin, G. Chen, I. Kolcu, Compiler-Guided Leakage Optimization for Banked Scratch-Pad Memories, IEEE Trans. on VLSI Systems, 13(10):1136-1146, Oct. 2005.
• N. Dhanwada, I. Lin, N. Vijaykrishnan, A Power Estimation Methodology for SystemC Transaction Level Models, Proc. of CODES-ISSS'05, Sep. 2005. PDF
• S. H. K. Narayanan, O. Ozturk, M. Kandemir. Workload Clustering for Increasing Energy Savings on Embedded MPSoCs, Proc. of SoCC’05, Sep. 2005. PDF PPT
• O. Ozturk, M. Kandemir, M. J. Irwin, On-Chip Memory Management for Embedded MPSoC Architectures Based on Data Compression, Proc. of SoCC’05, pp. 175-178, Sep. 2005.
• S. Srinivasan, F. Angiolini, M. Ruggiero, N. Vijaykrishnan, L. Benini, Simultaneous Memory and Bus Partitioning for SoC Architectures, Proc. of SoCC'05, Sep. 2005.
• G. Wang, M. J. Irwin, P. Berman, H. Fu, T. F. La Porta, Optimizing Sensor Movement Planning for Energy Efficiency, Proc. of ISLPED’05, Aug. 2005.
• G. Chen, M. Kandemir, M. J. Irwin, Exploiting Frequent Field Values in Java Objects for Reducing Heap Memory Requirements, Proc. of the 1st ACM/USENIX Conf. on Virtual Execution Environments (VEE'05), Jun. 2005.
• EJ. Kim, G. Link, K. H. Yum, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, C. R. Das, A Holistic Approach to Designing Energy-Efficient Cluster Interconnects, IEEE Trans. on Computers, 54(6):660-671, Jun. 2005.
• S. Yang, W. Wolf, N. Vijaykrishnan, Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations, IEEE Trans. on Computers, 54(6):714-726, Jun. 2005
• O. Ozturk, M. Kandemir, M. J. Irwin, Using Data Compression in an MPSoC Architecture for Improving Performance, Proc. of GLSVLSI’05, pp. 353-356, Apr. 2005.
• G. Chen, K. Malkowski, M. Kandemir, and P. Raghavan. Reducing power with performance constraints for parallel sparse applications. In Proc. High-Performance, Power-Aware Computing Workshop, Denver, Colorado, April 2005.
• P. Raghavan, M. J. Irwin, L. C. McInnes, B. Norris, Adaptive Software for Scientific Computing: Co-Managing Quality-Performance-Power Tradeoffs, Proc. of the NSF Next Generation Software Workshop, in conjunction with IPDPS'05, Apr. 2005.
• C. Liu, A. Sivasubramaniam, M. Kandemir, M. J. Irwin, Exploiting Barriers to Optimize Power Consumption of CMPs, Proc. of the Inter. Parallel and Distributed Processing Symp. (IPDPS’05), April 2005.
• W. Zhang, Y-F. Tsai, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, V. De, Leakage-Aware Compilation for VLIW Architectures, IEE Proceedings: Computers and Digital Techniques, 152(2): 251-260, Mar. 2005.
• I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, An Integer Linear Programming Based Tool for Wireless Sensor Networks, Journal of Parallel and Distributed Computing, 65(3):247-260, Mar. 2005.
• W-L. Hung, Y. Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, M. J. Irwin, Thermal-Aware Floorplanning Using Genetic Algorithms, Proc. of ISQED’05, pp. 634-639, Mar. 2005.
• O. Ozturk, M. Kandemir, M. J. Irwin, BB-GC: Basic-block Level Garbage Collection, Proc. of DATE’05, pp. 1032-1037, Mar. 2005.
• W-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Thermal-Aware Allocation and Scheduling for Systems-on-a-Chip Design, Proc. of DATE’05, pp. 898-899, Mar. 2005.
• Y-F. Tsai, N. Vijaykrishnan, Y. Xie, M. J. Irwin, Leakage-Aware Interconnect for On-Chip Network, Proc. of DATE’05, pp. 230-231, Mar. 2005.
• S. Yang, W. Wolf, N. Vijaykrishnan, Y Xie, Power Attack Resistant Crypto Design: A Dynamic Voltage and frequency Switching Approach, Proc. of DATE'05, pp. 3:64-69, Mar. 2005.
• S. Srinivasan, N. Vijaykrishnan, Simultaneous Partitioning and Frequency Assignment for On-chip Bus Architectures, Proc. of DATE'05, pp. 1:218–223, Mar. 2005.
• G. Link, N Vijaykrishnan, Hotspot Prevention Through Runtime Reconfiguration in Network-on-chip Designs, Proc. of DATE'05, pp. 1:648-649, Mar. 2005. PDF
• S. Kim, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Optimizing Leakage Energy Consumption in Cache Bitlines, Journal of Design Automation for Embedded Systems, 9(1):5-18, Mar. 2005.
• O. Ozturk, M. Kandemir, G. Chen, M. J. Irwin, Customized On-chip Memories for Embedded Chip Multiprocessors, Proc. of ASP-DAC’05, pp. 2:743-748, Jan. 2005.
• S. Srinivasan, A. Gayasen, N. Vijaykrishnan, T. Tuan, Leakage Control in FPGA Routing Fabric, Proc. of ASP-DAC'05, Jan. 2005.
• S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan, Y. Xie, Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies, Proc. of ASP-DAC'05, Jan. 2005.
• Y-F. Tsai, N. Vijaykrishnan, M. J. Irwin, Y. Xie, Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty, Proc. of VLSI Design, pp. 374-379, Jan. 2005.
• S. Yang S., W. Wolf, W. Wang, N. Vijaykrishnan, Y. Xie, Accurate Stacking Effect Macro-modeling of Leakage Power in Sub-100nm Circuits, Proc. of VLSI Design, pp. 165-170, Jan. 2005.

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