Chrysostomos A. Nicopoulos
My name is Chrysostomos A. Nicopoulos and I am a native of Cyprus, a small European island in the eastern Mediterranean sea.
I received my B.Sc. degree in Electrical Engineering (with a minor in Mathematics) from the Pennsylvania State University in 2003. I was ranked first out of 335 electrical engineering undergraduates, with a GPA of 4.0/4.0. I am also a graduate of the Schreyer Honors College, which oversees the Honors Program at Penn State University. In April 2003, I was the recipient of the highly prestigious Evan Pugh Scholar Award (upper 0.5 percent of class).
I received my PhD degree in Electrical Engineering (specialization in Computer Engineering) at Penn State in August 2007 (official degree conferral: December 2007). During my graduate studies, I worked in the Microsystems Design Laboratory (MDL) in the Computer Science and Engineering Department. My research advisor was Dr. Vijaykrishnan Narayanan.
As of 1 October 2007, I am a postdoctoral research associate in the Processor Architecture Laboratory (Laboratoire d'Architecture de Processeurs, LAP) at the Swiss Federal Institute of Technology, Lausanne (Ecole Polytechnique Federale de Lausanne, EPFL), in Switzerland.
Contact Information
- Email: chrys DOT nicopoulos AT epfl DOT ch
- Office: EPFL - IC - ISIM - LAP, INF 139, Station 14, CH-1015 Lausanne, Switzerland
- Phone: +41-21-69-38144 (Office), +41-21-69-32641 (Lab Secretary)
Research
The relentless shrinking of feature sizes into the nanometer realm has been accompanied by an equally staggering increase in transistor densities. As we sit at the threshold of the billion transistor era, new fascinating horizons have opened up in the field of digital systems design. Complex heterogeneous and homogeneous Systems-on-Chip (SoC) are steadily becoming ubiquitous, ranging from multimedia-enhanced chips for cable/satellite set-top boxes to Chip Multi-Processors (CMP). However, the increasing circuit complexity stemming from the inclusion of multiple cores on a single die has accentuated the role of the on-chip interconnects. The communication fabric is becoming dominant in the area, power and performance budgets of modern designs.
This profound realization has driven my research interests for the last couple of years. In particular, I have been actively involved in the research of packet-based Networks-on-Chip (NoC). I am particularly interested in the "golden" optimization triptych of AREA, POWER, and PERFORMANCE. I am currently exploring the following areas:
- High-performance, low-power, and fault-tolerant NoC router architectures for Chip Multi-Processors (CMP) and heterogeneous Multi-Processor Systems-on-Chip (MPSoC)
- Communication-centric many-core computer architectures
- On-chip network topologies
- Application mapping to NoC-based designs
- Performance evaluation of NoCs using workload traces
In addition to on-chip interconnects, my research interests also include:
- Computer architecture
- Digital systems design
- Three-dimensional (3D) system architectures
- Embedded systems design
- High-performance, power-efficient and reliable VLSI architectures
- Fault-tolerant SoC design and integration
Resume
Publications
Book Chapters
- T. Theocharides, C.A. Nicopoulos, K. Irick, N. Vijaykrishnan, and M. J. Irwin, "An Exploration of Hardware Architectures for Face Detection," in the VLSI Handbook, Second Edition, CRC Press, Taylor & Francis Group, Chapter 83, 2007.
Journal Articles
- F. Wang, C.A. Nicopoulos, X. Wu, Y. Xie, and N. Vijaykrishnan, "Variation-aware Task and Communication Mapping for MPSoC Architectures," submitted to the IEEE Transactions on Very Large Scale Integration (TVLSI) Systems in February 2008.
- D. Park, C.A. Nicopoulos, J. Kim, N. Vijaykrishnan, and C.R. Das, "Design Space Exploration for Fault-Tolerant On-Chip Interconnects," submitted to the IEEE Transactions on Dependable and Secure Computing (TDSC) in June 2007.
- C.A. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, N. Vijaykrishnan, C.R. Das, and M.J. Irwin, "On the Effects of Process Variation in Network-on-Chip Architectures," submitted to the IEEE Transactions on Dependable and Secure Computing (TDSC) in May 2007.
Conference Proceedings
- N. Soundararajan, A. Yanamandra, C.A. Nicopoulos, N. Vijaykrishnan, A. Sivasubramaniam, and M.J. Irwin, "Analysis and solutions to Issue Queue Process Variation," to appear in Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2008.
- R. Das, A.K. Mishra, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, R. Iyer, M.S. Yousif, and C.R. Das, "Performance and Power Optimization through Data Compression in Network-on-Chip Architectures," in Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA), February 2008.
- C.A. Nicopoulos, A. Yanamandra, S. Srinivasan, N. Vijaykrishnan, and M.J. Irwin, "Variation-Aware Low-Power Buffer Design," in Proceedings of the 41st Asilomar Conference on Signals, Systems, and Computers, pp. 1402-1406, 2007.
- F. Wang, C.A. Nicopoulos, X. Wu, Y. Xie, and N. Vijaykrishnan, "Variation-aware Task Allocation and Scheduling for MPSoC," in Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 598-603, 2007.
- D. Park, R. Das, C.A. Nicopoulos, J. Kim, N. Vijaykrishnan, R. Iyer, and C. R. Das, "Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects," in Proceedings of the Hot Interconnects Symposium, pp. 15-20, 2007.
- J. Kim, C.A. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, and C.R. Das, "A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures," in Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA), pp. 138-149, 2007.
- C.A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M.S. Yousif, and C.R. Das, "ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers," in Proceedings of the 39th Annual International Symposium on Microarchitecture (MICRO), pp. 333-344, 2006.
- D. Park, C.A. Nicopoulos, J. Kim, N. Vijaykrishnan, and C.R. Das, "A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects," in Proceedings of the 1st International Conference on Nano-Networks (Nano-Net), pp. 1-6, 2006.
- F. Li, C.A. Nicopoulos, T. Richardson, Yuan Xie, N. Vijaykrishnan, and M. Kandemir, "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory," in Proceedings of the 33rd Annual International Symposium on Computer Architecture (ISCA), pp. 130-141, 2006.
- J. Kim, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, M.S. Yousif, and C.R. Das, "A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks," in Proceedings of the 33rd Annual International Symposium on Computer Architecture (ISCA), pp. 4-15, 2006.
- D. Park, C.A. Nicopoulos, J. Kim, N. Vijaykrishnan, and C.R. Das, "Exploring Fault-Tolerant Network-on-Chip Architectures," in Proceedings of the International Conference on Dependable Systems and Networks (DSN), pp. 93-102, 2006.
- J. Kim, D. Park, C.A. Nicopoulos, N. Vijaykrishnan, and C.R. Das, "Performance Enhancement through Early Release and Buffer Optimization in Network-on-Chip Router Architectures," in Special Workshop on Future Interconnects and Networks on Chip at the Design, Automation and Test in Europe (DATE) Conference, 2006.
- T.D. Richardson, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, Yuan Xie, C.R. Das, and V. Degalahal, "A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks," in Proceedings of the 19th International Conference on VLSI Design, pp. 657-664, 2006.
- J. Kim, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, and C.R. Das, "A Fine-Grained Modular Architecture for System-on-Chip Networks," Technical Report, CSE-06-013, Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, 2006.
- J. Kim, D. Park, C.A. Nicopoulos, N. Vijaykrishnan, and C.R. Das, "Design and analysis of an NoC architecture from performance, reliability and energy perspective," in Proceedings of the Symposium on Architecture for Networking and Communications Systems (ANCS), pp. 173-182, 2005.
- J. S. Kim, C.A. Nicopoulos, N. Vijaykrishnan, Y. Xie, and E. Lattanzi, "A Probabilistic Model for Soft-Error Rate Estimation in Combinational Logic," in the 1st International Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems (PARTES), 2004.
- C.A. Nicopoulos, "Smart Antennas for Wireless Communications," Undergraduate Honors Thesis (under J.F. Doherty), Department of Electrical Engineering, The Pennsylvania State University, University Park, PA, 2003.
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Last updated: 2 May 2008 11:55 CET
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