Michael V. DeBole
My name is Michael DeBole and I am currently a PhD Candidate in the Department of Computer Science and Engineering at the Pennsylvania State University. I received my B.Sc. degree in Computer Engineering from The Pennsylvania State University in 2006 (with a minor in Engineering Leadership and Development).
I currently work in the Microsystems Design Laboratory(MDL) within the Computer Science and Engineering Department. I am co-advised by
Dr. Vijaykrishnan Narayanan and
Dr. Yuan Xie.
Research
As we begin to cross the threshold into the billion transistor era, Multiprocessor Systems-on-Chips (MPSoC) are becoming ever-present, driving advancement in multiple application domains ranging from entertainment to medical devices. Consequently, MPSoC designers must be able to optimize a multi-constrained set comprised of performance, power consumption, reliability and cost. At the same time, as feature sizes shrink into the sub-micron regime, physical limitations and manufacturing variability are resulting in unreliable, power-hungry chips. To combat this, system simulations which take into consideration the interplay of performance, thermal characteristics, variability, and reliability effects from real-life workloads, are becoming valuable when performing design space explorations of these next-generation architectures. However, the increase in complexity stemming from the need to profile complex modern processors, over extended periods of time, is placing a significant burden on the speed of traditional software simulators.
My work has been motivated by these challenges and has led me to begin investigating a Virtual Platform (ViP) framework on FPGAs which can significantly speed up system profiling through system emulation. Currently, I am working towards building a general framework for the ViP and using it to characterize a multi-core implementation of the IEEE-754 (SPARC V8) architecture. Once in place the ViP will then permit a thorough investigation into alternative architectures and mitigation techniques to achieve the golden "design" polyptych of POWER, PERFORMANCE, RESILIENCY, and COST.
In other work I have also developed hardware implementations of Neural Networks and Support Vector Machines as a means for detection and classification within images and video. In this work we utilized FPGA's as the primary means to realize these architectures.
My research interests also include
- FPGA Accelerators for Scientific Computing Applications
- FPGA's as a complete solution for system-on-chip (Hardware/Software Co-Design)
- VLSI design for low power, low cost, and high performance
- Embedded Systems
- Statistical learning theory and machine learning.
- Computer Architecture
Publications
Conference Papers
- David Atienza, Giovanni De Micheli, Luca Benini, Jose L. Ayala, Pablo G. Del Valle, Michael DeBole, Vijay Narayanan. "Reliability-Aware Design for Nanometer-Scale Devices" in Proceedings of the 13th Asia and South Pacific Design Automation Conference(ASP-DAC), January 2008. (*Invited Paper)
- Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, and Satish Mummareddy. "A Unified Streaming Architecture for Real Time Face Detection and Gender Classification," in Proceedings of the 21st Annual International Conference on Field Programmable Logic (FPL), August 2007.Talk
Journal Papers
- Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan and M.J. Irwin. "On-chip Bus Thermal Analysis and Optimization", accepted for publication in IEE Computer Design and Test, 2007.
Awards and Scholarships
- Recipient of the Lockheed Martin Graduate Fellowship
- Recipient of the C. Norwood Wherry Memorial Graduate Fellowship
- Lockheed Martin Design Award (Software Engineering)
Contact Information
- Email at PSU: debole AT cse DOT psu DOT edu
- Office : IST 351, IST Building, Penn State, University Park, PA 16802
- Phone : +1–814–863–1047 (Office)
Travel Schedule
| Depart Date | Return Date | Destination | Purpose |
| 2008 |
| March 4 | March 6 | Yorktown Hights, NY | GSRC Spring Meeting |
| June 7 | June 12 | Anaheim, CA | GSRC Meeting / DAC |
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