Rajaraman Ramanarayanan

I am a Doctoral candidate in the Elelctrical Engineering department at Penn State University. My advisors are Dr. Vijay Narayanan and Dr. Mary Jane Irwin in the Microsystems Design Laboratory. Prior to this I obtained my Bachelor of Engineering (B.E) degree in Electrical and Electronics Engineering at Annamalai University, India and Master of Science degree (M.S) in Electrical Engineering here at Penn State . My research is focussed on analysis and modeling reliable components in VLSI circuits. I have researched mainly in soft errors in logic circuits and flip-flops.

Publications

• R.Rajaraman, K. Ramakrishnan, N. Vijaykrishnan, Y. Xie, M. J. Irwin, "Temperature and Voltage Scaling effects on Electrical Masking", in the Proc. of Workshop on System Effects of Logic Soft Errors (SELSE), 2006.

• R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin, SEAT-LA: A Soft Error Analysis Tool for Combinational Logic, Proceedings of the International Conference on VLSI Design, Jan. 2006.

• Rajaraman Ramanarayanan, N. Vijaykrishnan, Yuan Xie and Mary Jane Irwin, and Kerry Bernstein, Soft Errors in Adder Circuits, presented at MAPLD International Conference, Sep. 2004.

• V. Degalahal, R. Ramanarayanan , N. Vijaykrishnan, Y. Xie and M. J. Irwin, The effect of threshold voltages on the soft error rate, Proceedings of the International Symposium on Quality Electronic Design, Mar. 2004.

• R. Ramanarayanan V. Degalahal, N. Vijaykrishnan, M. J. Irwin and D. Duarte, Analysis of Soft error rates in flip-flops and Scannable latches, Proceedings of the 16th Annual IEEE International ASIC/SOC Conference.

• R. Ramanarayanan N. Vijaykrishnan and M. J. Irwin, Characterization of Dynamic and Leakage Power in flip-flops and Scannable latches, Proceedings of the 15th Annual IEEE International ASIC/SOC Conference.

Resume

PDF PS TXT

Contact Information

Email : ramanara@ domain "cse.psu.edu"

Office : 354B IST Building, University Park, PA - 16802

Ph: 814 863 7325

to top