Wei-Lun Hung
I am a Doctoral student under Dr. Yuan Xie in the Microsystems Design Laboratory at the Computer Science and Engineering Department at Penn State. Prior to this I obtained my B.S in Information Management from National Taiwan University of Science and Technology and M.S. in Computer Science from National
TsingHua? University. I am currently a fourth year Ph.D. student and expect to graduate in Dec. 2006.
My research interests include VLSI algorithms for low-power design, computer arithmetic, and computer architecture. I am also interested in thermal-aware and variation-aware EDA tool designs.
Publications
* "Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing", by W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and Y. Tsai. International Symposium on Low Power Electronics and Design (ISLPED), August 2004.
PDF
PPT.
- "Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture", by W.-L. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan, and M. J. Irwin. International Conference on Computer Design (ICCD), San Jose, CA, October 2004.
- "Thermal-Aware Task Allocation and Scheduling for Embedded Systems", by W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Design, Automation and Test in Europe (DATE), Munich, Germany, March 2005.
- "Thermal-Aware Floorplanning Using Genetic Algorithms", by W.-L. Hung, Y. Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, and M. J. Irwin. International Symposium on Quality Electronic Design (ISQED), San Jose, CA , March 2005.
- "An ILP Formulation for Reliability-Oriented High-Level Synthesis", by S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Y. Xie, and W.-L. Hung. International Symposium on Quality Electronic Design (ISQED), San Jose, CA , March 2005.
- "Reliability-Centric Hardware/Software Co-design", by S. Tosun, N. Mansouri, E. Arvas, M Kandemir, Y. Xie, and W.-L. Hung. International Symposium on Quality Electronic Design (ISQED), San Jose, CA , March 2005.
- "Temperature-Aware Voltage Islands Architecting in System-on-Chip Design", by W.-L. Hung, G. Link, Y. Xie, N. Vijaykrishnan, N. Dhanwada and J. Conner. International Conference on Computer Design (ICCD), San Jose, CA , Oct 2005.
- "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors", by W.-L. Hung, G. Link, Y. Xie, N. Vijaykrishnan, and M. J. Irwin. International Symposium on Quality Electronic Design (ISQED), San Jose, CA , March 2006.
Conference Papers
- Authors. Title, in the proceedings of XYZ 2006 . PDF PPT. This work is supported in part by a few grants that I am thankful for.
- Authors. Title, in the proceedings of XYZ 2006 . PDF PPT. This work is supported in part by a few grants that I am thankful for.
Presentations
- Talk on XYX given at ABC on 31-Jan-2006 PPT
Resume
PDF DOC
Contact Information
- Email : whung AT cse DOT psu DOT edu
- Office : 351 , IST Building Penn State, University Park, PA ??16802
- Phone : +1 ??814 ??863 ??1047 (Office)
Links
Last updated: March 2006
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